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Welcome!
Library Technologies, Inc. develops and markets design and analysis
tools for integrated circuit design. The tools and products are
integrated together. They interface to popular chip designs flows. SolutionWare product line covers
characterization and modeling requirements for standard cells, IO
and memories including functional verification and design library
generation. Our circuit optimizer, CellOpt, performs transistor sizing
producing low power cells meeting timing requirements. To address
the challenges posed by process variation, YieldOpt identifies best
case/worst case process conditions under systematic and random variations
for each standard cell. It eliminates the need for Monte-Carlo simulations
and statistical timing analysis for digital designs. UnBlock helps
with the modeling and verification of custom digital designs. PowerTeam
provides vector based dynamic power simulation capability within Verilog
environment. ChipTimer reduces area and leakage, and improves the speed of any digital synthesizable
design by coupling netlist level timing optimization techniques with
on fly library generation capabilities of CellOpt.
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