Technical Papers and Product Literature

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	"Fast and Low Power Adders: What is the Magic?" You have come up with a fast adder architecture, and want to make sure that it implemented properly as well? This paper compares 4-bit Ripple Carry Adders and shows how a bad adder cell design may delay the addition by a factor of 2!
	"How cool and fast are they? A comparison of flip-flops" There are significant implications of flip-flop topology for toggle frequency and energy consumption. This paper compares different flip-flops using CellOpt by optimizing for the minimum clock period.
	"Verifying Critical Path Timing" There could be significant differences between Spice and timing reports generated by synthesis and timing analysis tools. This paper describes PathOpt and its interface to Design Compiler and PrimeTime for critical path verification.
	"Positional Sizing: A Recipe for High Speed and Low Power Cell Libraries" Positional sizing of parallel and series transistors has a big impact on cell delay, area and on switching energy. For the same effective delay of a uniformly sized cell, a positionally sized cell can be implemented in 30-50% smaller active area and dissipates 20-50% less energy.
	"Automated Cell Library Design is Ready for the Challenge" Cell Library Automation all the way through with Cellopt, Automatic Transistor Layout and Model Generation. Compares the impact of architecture on performance, area and power characteristics of standard cells.
	"Wire Load Independent Logic Synthesis and Timing Closure with Constant Replacement Delay Cell Libraries" Describes our Patent Pending Technology for synthesis without estimated wire loads.
	Product Information Brochure describing SolutionWare, CellOpt, YieldOpt, Powerteam, ChipTimer.

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