July 31, 2001 - Positional Sizing: A Recipe for High Speed and Low Power Cell Libraries

Positional sizing of parallel and series transistors has a big impact on cell delay, area and on switching energy. For the same effective delay of a uniformly sized cell, a positionally sized cell can be implemented in 30-50% smaller active area and dissipates 20-50% less energy.

For more information go to our Publications Department.