Current source based delay modeling is becoming popular as modeling of RC based interconnect becomes important. However this created a verification problem. Unlike previous generation of delay models where cell characterization model and delay calculation model assumed the same lumped capacitance approximation, current source models are used with distributed loads. As a result, it is important to be able to check the accuracy of the models under distributed load conditions. This is usually done for isolated instances of clock drivers in a manual fashion by comparing delay calculation to spice simulation. CCSTEST suite automates this process by generating test-bench circuits for every timing arc of each cell both at Spice level and verilog level, and with RC network load using a timing analyzer. Test-bench includes instances of the same cell as its fanout. This way both the driver model as well as the receiver models can be incorporated into the test-bench.
"Once a problem case has been identified by CCSTEST, the source of the error can be further narrowed by changing the fanout conditions or RC network loading or characterization setup if possible," said Dr. Mehmet Cirit, president of Library Technologies, Inc., "The process may also be used with non-RC load models, and may identify errors in driver and receiver models as well structural errors in existing libraries and missing timing arcs." CCSTEST is bundled with SolutionWare automatic characterization and modeling product. It is available for free to existing users of SolutionWare with support and maintenance agreement. Tests can be performed for core cells, IO's and memories. Run time of CCSTEST is a small fraction of the characterization time.
"Quite frequently cells are not described correctly in liberty libraries. They may have wrong values for some timing entries, or no entries for some critical timing arcs. Input capacitances may be wrong. Slope and load ranges may compromise delay calculation accuracy. They may be derated out of range. Liberty model may be incompatible with Verilog models," said Dr. Cirit, "We see such situations frequently with home made libraries, and even with commercial libraries. A proper exhaustive test environment is the only way to catch problems at their source." Library Technologies, Inc. also offers a test service for existing libraries using CCSTEST suite.
One of the challenges facing designer moving into leading edge processes is assuring themselves that the new current based models are capturing timing accuracy as best as possible. CCSTEST suite provides the right methodology and tools to address these concerns, by integrating the test environment into library creation process.
About Library Technologies, Inc.
Library Technologies, Inc. is a private company, developing and marketing various integrated circuit design and analysis tools. Its products include SolutionWare which does cell, IO and memory characterization and modeling, Cellopt for cell level timing and power optimization, ChipTimer for design optimization and timing closure, PowerTeam for Verilog based dynamic gate level power simulation and finally YieldOpt for process variation analysis. More information can be found at here.
Contacts:
Mehmet Cirit
President
Library Technologies, Inc.
(408) 741-1214
mac@libtech.com